The present invention is directed to the manufacture of a field effect transistor wherein a common metallization is applied for the ohmic contacts of source and drain and the Schottky contact of the gate.
In field effect transistors (for example, MESFET, HEMT), the gate is localized as close as possible to the source. The source metallization forms an ohmic contact (a conductive transition between metal and semiconductor) on the semiconductor material. The metallization for the gate forms a Schottky contact (i.e. a junction between the metal electrode and the semiconductor material that inhibits in one current direction). The gate metal is therefore generally to be separately applied from the ohmic metal employed for the source and drain. As a result of the alignment of the two types of metal for the three electrodes relative to one another, a scatter in the positioning and, thus, a scatter of the electrical parameters of the transistor arises as a result of the alignment precision of the lithography technique.
Given alloyed ohmic contacts, two photolithographic steps are employed for a germanium implantation and a common metallization in what is referred to as DIOM technique (DIOM=double implantation one metallization). This is disclosed, for example, by European reference EP 0 034 729 B1. A version of this DIOM technique manages with one photolithography step having two depositions of layers in situ. In this method disclosed by German reference DE 42 19 935, germanium for the contacts of source and drain is first vapor-deposited obliquely onto a mask with openings in the regions of source, gate and drain such that the metallization for source and drain is produced but the region of the gate remains free. Subsequently, the metallization provided for the gate is applied in an anisotropic, perpendicular vapor-deposition. Disadvantages of this method are that the lower parts of the sidewalls of the mask employed are not reached in the vapor-deposition and the lateral angles between these sidewalls and the semiconductor surface are therefore not covered, that the utilization thereof at high temperatures encounters its method-conditioned limit due to the employment of the subsequent alloying process, and that the sintered gate contact has a natural residual roughness of the alloy front, this limiting the management of the cut-off voltage of the FET.
It is also known to manufacture FETs with unalloyed ohmic contacts on highly doped InGaAs layers (doping density greater than 10.sup.19 cm.sup.-3). Such layers, namely, form such a thin and low barrier that enough electrons can flow from each metal contact into this InGaAs layer. Since InGaAs is epitaxially deposited and covers the substrate surface-wide, the InGaAs layer must be selectively removed (etched off) in the gate region so that the gate metal can, for example, form a Schottky contact with the GaAs and can control the current in more deeply disposed layers (channel layer). In conventional methods of the species for HEMTs (high electron mobility transistor) with InGaAs contact layer (as cover layer at the upper side of the component), two photolithography steps for two different metal depositions are likewise required. Publications are, for example for an arrangement on GaAs substrate, the article by M. Nihei et al, "Nonalloyed Ohmic Contacts for HEMTs Using n.sup.+ -InGaAs Layers Grown by MOVPE", in IEICE Trans. Electron. E77-C, 1431-1436 (1994), and, on InP-substrate, the article by N. Yoshida et al. "Low Noise AllnAs/InGaAs HEMT using WSi ohmic contact" in Electronics Letters 30, 1009-1010 (1994). Alternatively thereto, two photolithography steps can be employed for a selective etching and for a common aluminum deposition, as disclosed, for example, in the article by S. Kuroda et al, "A New Fabrication Technology for AlGaAs/GaAs HEMT LSI's Using InGaAs Nonalloyed Ohmic Contacts", in IEEE Transact. Electr. Dev. 36, 2196-2203 (1989).
Japanese reference JP 1-265571 discloses a method for manufacturing a Field Effect Transistor (FET) wherein a highly doped contact layer is applied on a channel layer, this contact layer is removed in the region of the gate, spacers on the channel layer and adjoining the remaining parts of the contact layer are produced upon employment of an auxiliary layer, and, after the removal of the remaining auxiliary layer and the lateral application of photoresist, a metallization is applied that decomposes in metallizations that are provided for source, gate and drain and that are electrically insulated from one another by the spacers. In this method, only one Al layer need be applied by vapor-deposition. Given employment of only one photolithography step, the gate-drain spacing is limited by the possibilities in the manufacture of the spacers, i.e. the breakdown voltage that can be achieved is correspondingly low. Given employment of two lithography steps for structuring the dielectric auxiliary layer (double spacer), the scatter of the parameters of the transistor becomes greater as a consequence of the required adjustment for the photolithography. German reference DE 39 13 540 A1 discloses a method for the manufacture of field effect transistors wherein a structuring layer is obliquely vapor-deposited onto a mask, so that an opening with small dimensions provided for the structuring of a gate electrode is formed in the mask opening. Germanium is preferably employed as material for the structuring layer. A dielectric material is likewise recited as being suitable.